1. Field of the Invention
The present invention relates to a fabrication process for DRAM, and in particular to a bitline structure for DRAM and method of forming the same.
2. Description of the Related Art
Random access memory (RAM) is a volatile memory, usually categorized into static RAM (SRAM) and dynamic RAM (DRAM). SRAM stores information by the conductive state of the transistors in the memory cells, while digital signals from DRAM are determined by the charging states of capacitors in the memory cells. In RAM, information access is controlled by word lines connecting gates and bitlines that connect source/drain.
Conventional bitlines are mostly metal, with silicide preferred. Tungsten silicide and tungsten are the most widely used, as they exhibit high melting point, stability and low resistance.
FIG. 1 illustrates a cross section of a conventional bitline structure. 10 represents a substrate, 12 represents the dielectric layer, and 14, 20, 22, 24 are bitlines of metal, for example, tungsten. 16 represents a contact to bitline and 18 represents a peripheral contact.
The process for forming the above bitlines is shown as a flowchart in FIG. 2. A contact to bitline is first formed in a dielectric layer of a semiconductor substrate by photolithography and etching in step S10. Next, conductive material is filled in the contact to bitline in step S20. Etching back is then carried out in step S30 to lower the surface of the conductive material below the surface of the dielectric layer. Then, a peripheral contact is formed by photolithography and etching in step S40A. Exposure and etching are then performed to define bitlines. Next, a conductive material, such as tungsten, fills the contact to bitline and the peripheral contact to form bitlines. After completion of the bitlines, chemical mechanical polishing polishes the surface of the bitlines to create a smooth surface as illustrated in FIG. 1.
Shortcomings of the conventional process described above are overlapping bitlines due to high integration, causing shorts easily, illustrated as P between bitlines BL1 and BL2 in FIG. 6B. This adversely affects production yield.
Accordingly, an object of the invention is to provide a method for forming bitlines for DRAM that solve the overlapping problems and improve production yields.
A major feature of the method forming bitlines for DRAM of the present invention is formation of a dielectric layer to cover the contact to bitline, followed by simultaneous formation of a peripheral contact and a bitline trench in a position relative to the contact to bitline in the dielectric layer. Alternatively, a bitline contact landing having a widened area is formed on the contact to bitline, followed by formation of a bitline trench. Conductive material then fills the bitline trench to form a bitline.
The method for forming bitlines for DRAM includes providing a semiconductor substrate having a first dielectric layer formed thereon and a contact hole through the dielectric layer, filling the contact hole with a conductive material to form a first conductive layer and etching back the first conductive layer to below the first dielectric layer, increasing the opening of the contact hole by isotropic etching to form a first opening, filling the first opening with conductive layer to form a bitline contact landing, forming a second dielectric layer on the entire first dielectric layer to cover the bitline contact landing, forming a peripheral contact hole and defining a first bitline trench simultaneously to expose the bitline contact landing, defining a second bitline trench in the second dielectric layer to expose the peripheral contact hole, and filling the peripheral contact hole, the first bitline trench and the second bitline trench with conductive material to form a peripheral contact, a first bitline and a second bitline.
According to another embodiment of the invention, the method for forming bitlines for DRAM comprises providing a semiconductor substrate having a first dielectric layer formed thereon and a contact hole through the dielectric layer, filling the contact hole with a conductive material to form a first conductive layer, forming a second dielectric layer on the first dielectric layer to entirely cover the first conductive layer, forming a peripheral contact hole and defining a first bitline trench in the second dielectric layer, defining a second bitline trench in the second dielectric layer to expose the peripheral contact hole, and filling the peripheral contact hole, the first bitline trench and the second bitline trench with conductive material to form a peripheral contact, a first bitline and a second bitline.
According to the invention, the bitline structure comprises a substrate, a first dielectric layer, formed on the substrate, a bitline contact hole, through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the entire first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.
According to another embodiment, the bitline structure further comprises a bitline contact landing, formed in the first dielectric layer between the contact to bitline and the bitline for connecting both.
A detailed description is given in the following embodiments with reference to the accompanying drawings.